Priority is claimed to Japanese Patent Application Number JP2004-086555 filed on Mar. 24, 2005, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a circuit device and a manufacturing method thereof and, more specifically, to a circuit device and a manufacturing method thereof which are capable of enhancing positional accuracy of an exposed part of a conductive pattern.
2. Background Art
Heretofore, there have been demands for the downsizing, the thinning, and the reduction in weight of circuit devices to be incorporated in electronic devices since the circuit devices have been adopted to cellular telephones, portable computers, and the like.
Taking a semiconductor device as an example for the circuit devices, a circuit device so-called a chip size package (CSP) having a size being equivalent to that of a chip has been recently developed.
However, a typical CSP applies a glass epoxy substrate as an interposer that precludes downsizing and achieving a thin profile of the CSP. To solve this problem, the applicant of the present invention has developed a method of manufacturing a circuit device as shown in FIG. 13A to FIG. 14C, in which a mounting substrate is not required. This technology is described for instance in Japanese Unexamined Patent Publication No. 2003-155591.
The method of manufacturing a circuit device will be described with reference to FIG. 13A to FIG. 14C. As shown in FIG. 13A, conductive foil 110 is prepared and etching resist 111 is patterned in a desired shape on a surface thereof. Next, as shown in FIG. 13B, isolation trenches 112 are formed on the surface of the conductive foil 110 by performing half etching. Then, as shown in FIG. 13C, resin film 115 is coated on the surface of the conductive foil after peeling off the etching resist 111. Next, as shown in FIG. 13D, open portions 130 are formed on the surfaces of conductive patterns 113. Such formation of the open portions 130 can be achieved by performing a removing method using a laser, a lithographic process, and the like. Here, errors upon formation of the open portions 130 are taken into account, and the peripheral portion of each of the open portions 130 and the peripheral portion of each of the conductive patterns 113 are separated from each other by providing a predetermined distance α.
As shown in FIG. 14A, sealing resin 120 is formed after a semiconductor element 116 and a chip element 117 are electrically connected to the conductive patterns 113. Subsequently, as shown in FIG. 14B, the respective conductive patterns 113 are electrically isolated by removing a rear surface of the conductive foil. Thereafter, as shown in FIG. 14C, external electrodes 121 are formed on rear surfaces of the conductive patterns 113 and then covering resin 122 is formed thereon. In the above-described process, it is possible to form a conventional circuit device.
However, the circuit device and the manufacturing method described above have the following problems.
As shown in FIG. 13D, the conductive patterns 113 have been formed in unnecessarily large planar sizes due to redundant design in consideration of errors upon formation of the open portions 130. Such redundant design has caused an increase in size of the entire circuit device. Moreover, a high-precision and expensive exposure machine or laser irradiator is required to form the open portion 130 in an accurate position. Such requirement has increased manufacturing costs.
Moreover, since an adhesive for attaching the chip element 117 or the like has been formed on the open portion 130 of the resin film, the adhesive has been formed into a constricted shape. Such a form has precluded reliability against thermal stress.
The present invention was made in view of the above-described problems, and a main objective thereof is to provide a circuit device and a manufacturing method thereof in which a positional accuracy for a conductive pattern is high with low cost.